A DFT (Device for Testability) technique for testing semiconductor chips has been widely used to determine the quality of a chip. Also, a scan test technique has been conventionally used as an important technique in chip testing.
In general, a flip flop circuit stores and sequentially transfers a received signal in response to a clock signal or a pulse signal. A flip flop circuit with a scan function receives a scan test signal and tests a logic circuit in a corresponding semiconductor circuit using the scan test signal. Accordingly, such a flip flop circuit with a scan function is designed according to the needs of the test to be performed upon a logic circuit.
Meanwhile, the DFT is a chip test device using scan cells and is used when an internal scan chain is formed in order to reduce a time for testing of a semiconductor chip. Conventionally, a scan cell method and a BIST (Built-in-Test) method are mainly used with a DFT. Here, the scan cell method is performed to make the testing of a chip more robust by forming flip flops using a series of shift registers. Test data is applied to the flip flops or measuring values stored in the flip flops through a shift path (that is, scan path) when testing the chip.
FIG. 1 is a circuit diagram of a conventional master-slave flip flop 100.
Referring to FIG. 1, the conventional master-slave flip flop 100 with a scan function includes a first AND gate 102 which receives a data signal D and an inverted scan enable signal ˜SE and performs an AND operation of the data signal D and the inverted scan enable signal ˜SE; a second AND gate 104 which receives a scan input signal SI and a scan enable signal SE and performs an AND operation of the scan input signal SI and the scan enable signal SE; a first NOR gate 106 which performs a NOR operation of an output of the first AND gate 102 and an output of the second AND gate 104; a first tri-state inverter 108 which inverts an output of the first NOR gate 106 when an inverted clock signal CKB is logic high; a first inverter 110 which inverts an output of the first tri-state inverter 108; a second tri-state inverter 112 which inverts an output of the first inverter 110 and transfers the inverted output to an input terminal of the first inverter 110 when a clock signal CK is logic high; a second inverter which inverts an output of the tri-state inverter 114; a third tri-state inverter 114 which inverts an output of the first inverter 110 when the inverted clock signal CKB is logic high; a second inverter 116 which inverts an output of the third tri-state inverter 114; a fourth tri-state inverter 118 which inverts an output of the second inverter 116 and transfers the inverted output to an input terminal of the second inverter 116 when the clock signal CK is logic high; and a third inverter 120 which inverts and amplifies an output of the inverter 116.
If the scan enable signal SE is logic low, the data signal D is output through the first AND gate 102 and the NOR gate 106. If the clock signal CK is logic low, the data signal D is transferred to a first latch unit 122 including the inverters 110 and 112. If the clock signal CK is logic high, the first tri-state inverter 108 is turned off and the data signal D is stored in the first latch unit 122. Then, the third tri-state inverter 114 inverts the data signal D stored in the first latch unit 122 and transfers the inverted data signal to a second latch unit 124 including the inverters 116 and 118, in synchronization to the clock signal CK of logic low. The data stored in the second latch unit 124 is transferred to a logic circuit of a semiconductor chip via the third inverter 120. The second latch unit 124 maintains the stored data until the stored data is synchronized to a following clock signal.
However, the conventional master-slave flip flop 100 shown in FIG. 1 is not suitable for high-speed operation since a D-to-Q delay (delay time between an input and an output) is long.
Compared with such a clock-based master-slave flip flop, in a pulse-based flip flop, since a D-to-Q delay is short, it is possible to reduce loading, a C-to-Q delay (delay time between a clock transition and an output) as well as the D-to-Q delay, and to achieve size reduction of the flip flop.
However, since a conventional pulse-based flip flop with a scan function has a complicated circuit configuration, it requires a large area.